The subject of this invention is a process for creating an integrated circuit stage where fine patterns and wide patterns, particularly semi-conductors, coexist.
The technique is known of etching semi-conductor layers so as to leave remaining only isolated patterns, which will be part of the integrated circuit. This is achieved particularly by depositing a hard mask on the semi-conductor layer, which is subsequently removed from the portions to be etched in such a way that it shields the patterns which are to be protected against etching. Use is generally made of another etching stage in respect of removing the mask at unnecessary points, after depositing resin over the portions of the mask which need to be protected. The resin is deposited in a continuous layer which is exposed, in other words subjected to conditions which sensitise it, either over the portions for protection by the mask, or over the other portions, depending on whether a so-called xe2x80x9cnegativexe2x80x9d or xe2x80x9cpositivexe2x80x9d resin is concerned. A resin development stage then removes it from places other than the portions for protection by the mask. Finally the remainder of the resin is removed when the mask has been etched.
Two main processes exist for exposing the resin: radiation, particularly by ultraviolet light or X-rays, and particle bombardments, particularly by electrons or also ions, etc., often carried out by beam scanning. Depending on their composition, resins are in practice sensitive to one or the other of these processes. Radiation allows the resin to be exposed collectively and the patterns to be marked out therefore in one go. On the other hand, it may be noted that they do not allow semi-conductor patterns to be obtained subsequently with great precision of dimension, which makes them unsuitable when the patterns it is required to produce are fine, since the inaccuracies then become excessive.
Particle bombardments make it possible on the other hand to achieve patterns with great precision but only expose the resin slowly, the beam having to be moved gradually over the whole surface to be exposed. When wide and fine patterns coexist, the general use of particle bombardment, made necessary however by the presence of fine patterns, leads to inordinate fabrication times.
It is therefore useful in this technical sector to allow the joint use of radiation and particle bombardments in forming the wide and fine patterns respectively (typically, 100 nm and 20 nm widths respectively) of the integrated circuit stage, without the application of radiation having a damaging effect on the formation of fine patterns, and reserving particle bombardment for fine patterns so as not to increase the stage fabrication time more than is necessary.
An article by Tedesco and others xe2x80x9cResist process of hybrid (electron-beam/deep ultraviolet) lithographyxe2x80x9d which appeared in the Journal of Vacuum Science and Technology, B16 (6), Nov.-December 1998, pp 3676-3683, mentions the possibility of using a xe2x80x9cmixedxe2x80x9d resin, able to be exposed both to radiation and to particle beams; but such resins are not optimum either for one exposition process nor for the other.
The use of hard masks in place of resin has also been proposed so as to allow fine patterns to be etched with precision; but resins remain more convenient to use.
The patent EP-A-0 779 556 relates to a process for creating an integrated circuit stage including patterns, particularly semi-conductors, some first of which have widths above a threshold and some second of which have widths below the threshold, consisting in depositing a layer of pattern material on a substrate, a mask on the layer of pattern material, then an upper layer on the mask, a first resin which is exposed and developed subsisting only on the first patterns still to be formed, in etching the upper layer, in eliminating the first resin, in depositing a second resin which is exposed and developed subsisting on the second patterns still to be formed, in etching the mask where it is visible, in etching the layer of pattern material, thus forming the first and second patterns, where it is visible, and in removing the second resin.
Some of the first patterns may be adjacent to some of the second patterns. In accordance with what has already been disclosed, the first resin is generally sensitised by exposure to radiation and the second resin is sensitised by exposure to particle bombardment. Prior to initiating the etching of the upper layer in the first case, the etching of the pattern material layer in the second case, the exposed resin is developed.
The upper layer is to advantage made of the pattern material and completely removed when the pattern material layer is etched.
It is intended to perfect a process like the one in this patent EP-A-0 779 556 using steps which consist in etching the mask where it is visible after etching the upper layer, then in depositing a second mask after removing the first resin, and in etching the second mask where it is visible after depositing the second resin.
Indeed, the second mask may form flanks around residues of the first mask deposited on the pattern material layer, and these flanks subsist until the pattern material layer is etched.
One effect of this particular process is that the first patterns may be formed with a broadened base under the flanks of the second mask, which is advantageous if these patterns are MOS transistors.
Another effect is that the flanks maintain the width of the wide patterns by protecting them against the lateral attacks which would have caused them to contract during etching of the pattern material layer.